TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 440

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

(d) Isochronous transfer type
(d-1) Isochronous transmission mode
•
•
each frame.
transfer type transfer only 2 phases (token, data) and it does not use handshake
phase. And data PID for data phase is always DATA0 because of this transaction does
not support toggle sequence. Therefore, UDC does not confirm when data PID is in
receiving mode.
completed transfer use receiving SOF token. The UDC uses FIFO that is divided into
two in Isochronous transfer type.
given below.
in endpoint is transmitted by IN token in the next frame.
condition or Y condition. The flow below is explained as X Condition (packet A), Y
Condition (packet B) in present frame.
X. FIFO for storing data that transmits to host in present frame
Y. FIFO for storing data for transmitting host in next frame
Isochronous transfer type is guaranteed transfer by data number that is limited to
However, this transfer does not retry when an error occurs. Therefore, Isochronous
Isochronous transfer type processes data every frame. Therefore, all transaction for
The transaction format for Isochronous transfer type format in transmitting is
Control flow
Isochronous transfer type is frame management. And data that is written to FIFO
Below are two conditions in FIFO of Isochronous transmission mode transferring.
FIFO that is divided into two (packet A and packet B) conditions is whether X
X and Y conditions change one after the other by receiving SOF.
Control flow in the UDC when receiving IN token is shown below.
1. Token packet is received and address endpoint number error is confirmed, and it
2. Condition of status register is confirmed.
3. Data packet is generated.
4. CRC bit (counted transfer data of FIFO from first to last) is attached to last.
Token
Data
(DATASET register bit = 1)
(DATASET register bit = 0)
INVALID condition: State returns to IDLE.
Data packet is generated. At this point, data PID is always attached to DATA0.
Next, data is transferred from FIFO (X condition) of packet A in UDC to SIE and
DATA packet is generated.
checks whether the relevant endpoint transfer mode corresponds with the IN
token. If it does not correspond, the state returns to IDLE.
: IN
: DATA0
92CF26A-438
TMP92CF26A
2009-06-25