TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 442

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

Not receive SOF
Transmit data
Generate DATA PID
• Attach DATA0
• Confirm DATASIZE register
Confirm Token packet
Attach CRC
Figure 3.16.10 Control Flow in UDC (Isochronous transfer type (Transmission))
Loss data
OK
OK
Not renewal frame number
• Confirm STATUS register (status)
• PID
• Address
• Endpoint
• Transfer mode
• Error
Confirm Status
IDLE
IDLE
CRC Error
Set LOST to FRAME register
Frame number unknown
Shift FIFO BANKs
every receive SOF
Receive SOF
without transmitting data
ReceiveSOF
Asset
Renew frame number
SOF
NG
OK
92CF26A-440
Invalid
Clear X condition (A)
Set FULL to STATUS
BANK B transaction
BANK A transaction
• Clear transmitting FIFO BANK A in preceding frame
• Clear DATASET register’s BANK A bit
• Set DATASET register’s BANK B bit
• Set STATUS to READY
• Wait data for transmitting next frame (BANK A)
• Clear transmitting FIFO BANK B in preceding
• Clear DATASET register’s BANK B bit
• Set DATASET register’s BANK A bit
• Set STATUS to READY
• Wait data for transmitting next frame (BANK B)
(Finish a write in previous frame)
frame
(Finish a write in previous frame)
TMP92CF26A
2009-06-25