TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 446

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

3.16.7
Bus Interface and Access to FIFO
(1) CPU bus interface
single packet mode, FIFO capacity that is implemented by hardware is used as large
FIFO. In dual packet mode, FIFO capacity is divided into two and used as two FIFOs.
It is also used as an independent FIFO. Even if the UDC is transmitting and
receiving to USB host, it can be used as an efficient bus by possible load to FIFO.
to “0”, FIFO register runs in single mode.
Sample: Where endpoint 1 is used to dual packet of payload 64 bytes.
The UDC prepares two types of FIFO access, single packet and dual packet. In
But control transfer type receives only single packet mode.
EPx_SINGLE signal in dual packet mode must be fixed to “0”. If this signal is fixed
EP1_FIFO size
EP1_SINGLE signal
EP1 Descriptor setting
Direction
Max payload size
Transfer mode
92CF26A-444
:
:
:
:
:
Prepare 128 bytes
Hold 0
Optional
64 bytes
Optional
TMP92CF26A
2009-06-25