TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 448

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

If transmitting number reach to payload,
UDC sets "1" to relevant bit
of DATASET register.
Transmitting number > payload
• Write payload number in relevant endpoint
• Total = Total − payload
Wait transmission event
Figure 3.16.14 Transmitting Sequence in Single Packet Mode
Below is the transmitting sequence in single packet mode.
When receiving In-Token from USB Host,
UDC transmits data.
DATASET register
Clear relevant bit of DATASET register
• Check bit of EPx_DSET_A
92CF26A-446
transmitting
Distinction
number
IDLE
EOP register
Transmitting number ≤ payload
• Write transmitting number in relevant endpoint
• Total = 0
Write 0 to only bit of relevant endpoint
Transmission event
Return to IDLE
• Accessing to EOP register is needed in
• Acessing endpoint0 is used for showing
UDC sets "1" to relevant bit
of DATASET register.
transmitting short packet.
closing control transfer.Therefore,always
access to endpoint 0 in closing control
transfer whether short packet or not.
TMP92CF26A
2009-06-25