TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 452

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

3.16.8
detecting of hardware reset, detecting of USB bus reset, and enumeration answer.
USB Device answer
The USB controller (UDC) sets various register and initialization in the UDC in
Each condition is explained below.
(1) bus reset detect condition.
(2) Detail of STATUS register
register, and it prepares enumeration operation from USB host. After detecting a
USB reset, the UDC sets ENDPOINT0 to control transfer type 8-byte payload and
default address for using default pipe. Any endpoint other than this is prohibited.
each endpoint in the UDC.
changing conditions for each transfer type.
the results of various transfers. It can be confirmed previous result that is transferred
to endpoint by confirming from external of UDC.
is showed is different for each transfer mode. Therefore, please refer to each transfer
mode column below.
When the UDC detects a bus reset on the USB signal line, it initializes internal
Status register that has been prepared for each endpoint shows the condition of
Each condition affects the various USB transfers. Refer to chapter 5 for the
EPx_STATUS register value is 0 to 3, and its shows conditions are shown. 0 to 4 are
These conditions mean that the endpoint is operating normally. The meaning that
Register name
ENDPOINT STATUS
0
1
2
3
4
READY
DATAIN
FULL
TX_ERR
RX_ERR
92CF26A-450
EP0
Except for EP0
Initial value
1CH
00H
TMP92CF26A
2009-06-25