TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 483

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

SPIMD
(820H)
modify-write
operation
cannot be
performed
(821H)
A read-
3.17.2
Bit Symbol
Read/Write
Reset State
Function
Bit Symbol
Read/Write
Reset State
Function
Note: The SD card of the TMP92CF26A supports a baud rate of up to 20 Mbps in SPI mode. The baud rate should be
data buses.
(1) SPIMD (SPI Mode Select register)
(a) LOOPBACK
The SPIMD register specifies the operating mode, clock operation, etc.
This section describes the SFRs of the SPIC. These are connected to the CPU with 16 bit
adjusted with the operating frequency of the CPU (f
internally connected to the SPDI input. This setup can be used for testing.
transmission or receptionis in progress.
this bit.
Special Function Registers (SFRs)
LOOPBACK
Test Mode
0:Disbale
1:Enable
Setting the XEN and LOOPBACK bits to 1 enables the internal SPDO output to be
Also, a clock sigal is generated from the SPCLK pin, regardless of whether data
Data transmission or reception must not be performed while changing the state of
Software
Reset
0: Don’t care
1: Reset
LOOPBACK
SWRST
15
W
7
0
0
Start Bit for
Transmission /
0: LSB
1: MSB
Reception
SYSCK
0: Disable
1: Enable
Data Transmission
MSB1ST
Figure 3.17.3 LOOPBACK Bit Configuration
Data Reception
XEN
R/W
R/W
14
6
1
0
Figure 3.17.2 SPIMD Register
SPDO Pin
State
When Not
Transmitting
0: Fixed to 0
1:Fixed to 1
DOSTAT
13
5
1
SPIMD Register
92CF26A-481
SPIMD<LOOPBACK>
Y
12
4
B
A
SYS
Synchronizati
-on Clock
Edge Select
for
Transmission
0: Falling
1: Rising
) so that it does not exceed 20 MHz.
edge
edge
TCPOL
11
3
0
Select Baud Rate(Note1)
000: Reserved
001: f
010: f
011: f
Synchronizat
ion Clock
Edge Select
for Reception
0: fall
1: rise
CLKSEL2
SPDI pin
SPDO pin
RCPOL
10
2
1
SYS
SYS
SYS
0
/2
/3
/4
R/W
Data
Inversion for
Transmissio
n0: Disable
1: Enable
CLKSEL1
TDINV
R/W
1
9
0
0
101: f
110: f
111: f
100: f
SYS
SYS
SYS
SYS
Data Inversion
for Reception
0: Disable
1: Enable
TMP92CF26A
/16
/64
/256
CLKSEL0
/8
RDINV
2009-06-25
0
8
0
0