TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 489

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

(j) RXMOD
system operation.
the data transmission is completed.
reception, it is prohibited to change the reception mode from Sequential to UNIT, or
vice versa.
interrupt is generated when the received data is loaded from the receive shift register
to the receive data register (SPIRD).
interrupt is generated when the size of received data stored in the receive FIFO
reaches 16 or 32 bytes.
Important Note:
When the SPICT<TEX> bit is set to 1, the state of any bits must not be changed until
For UNIT-mode reception, the receive FIFO buffer is disabled and the RFUL
For sequential-mode reception, the 32-byte receive FIFO is enabled and the RFUL
When in UNIT mode (TXMOD = 0), the following restriction is imposed on the
This bit selects the data reception mode from UNIT and Sequential modes. During
Sample Program 1:
Wait:
Sample Program 2 (Recommend):
LD
DI
SET 3,
BIT 1,
JPZ,
RES 3,
EI
Check the transmission end flag. (SPIST<TEND> = 1)
LD
DI
SET 3,
RES 3,
EI
(SPITDx), A
(SPICT)
(SPICT)
(SPITDx), A
(SPICT)
(SPIST)
Wait
(SPICT)
92CF26A-487
; Load “A” the tranmit data
; Disable the interrupt
; Start transmission be setting the TXE bit to 1
; Disable the transmission by clearing the TXE bit to 0
; Enable the interrupt
; Load the tranmit data
; Disable the interrupt
; Start transmission by setting the TXE bit to 1
; Wait for the completion of the transmission
; Disable the transmission by clearing the TXE bit to 0
; Enable the interrupt
TMP92CF26A
2009-06-25