TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 490

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

(1) UNIT transmission
(2) Sequential transmission
(3) UNIT reception
(4) Sequential reception
(5) UNIT transmission and
(6)Sequential transmission
Operatiing Mode
reception
and reception
x: Don’t care
(k) RXE
[Data Transmission/Reception Modes]
This SPI Controller supports six operating modes as listed below.
These are specified by the FDPXE, RXMOD, RXE, TXMOD, TXE bits.
UNIT-size data.
more UNIT data is additionally received.
the 32-byte FIFO buffer becomes full. The state of this bit can be changed even during
the data reception. If this bit is cleared to 0 during a data reception, the reception is
stopped after completing the reception of the UNIT data currently being received.
In the UNIT–mode reception, writing a 1 to this bit enables the reception of only one
When reading the receive data register (SPIRD) while this bit is kept enabled, one
In Sequential mode, writing a 1 to this bit enables the sequential data reception until
<FDPXE>
0
0
0
0
1
1
Table 3.17.2 Data Transmission Reception Modes
<TXMOD>
0
1
x
0
1
x
Bit Settings
<TXE>
92CF26A-488
1
1
1
1
x
x
<RXMOD>
x
x
0
1
0
1
<RXE>
1
1
1
1
x
x
Transmit the SPITD data per UNIT
Transmit the FIFO data sequentially
Receive only one UNIT-size data
Automatically receive data if FIFO buffer
has any empty space
Transmit/receive one UNIT-size data with
the addresses of transmit/receive data
aligned on UNIT-size boundaries
Transmit/receive data sequentially with the
addresses of transmit/receive data aligned
on UNIT-size boundaries
Description
TMP92CF26A
2009-06-25