TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 493

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

data reception can be selected by writing a 0 to the SPICT<RXMOD> bit.
a receive operation of one UNIT data. Then, the transmission is terminated after storing
the received data into the receive data register (SPIRD). To perform one-UNIT data
reception, read the SPIRD register after writing a 0 to the SPICT<RXE> bit. If the SPIRD
register is read again when the SPICT<RXE> bit is set to1, one-UNIT data is additionally
received. During the data reception, it is prohibited to change the reception mode from
Sequential to UNIT, or vice versa.
loaded into the SPIRD register from the receive shift register.
FIFO has any empty space. The Sequential mode is selected by writing a 1 to the
SPICT<RXMOD> bit.The 32-byte receive FIFO is disabled in this mode. In this reception
mode, the data reads from the receive FIFO must be performed in 16-byteunits. Otherwise,
the RFUL interrupt is not properly generated.
receive FIFO becomes full (32 bytes). Therefore, the reception continues sequentially
without stopping at every UNIT-sized reception. During the data reception, it is prohibited
to change the reception mode from Sequential to UNIT, or vice versa.
completingthe reception of the UNIT data currently being received.
or 32 bytes. The REND interrupt is generated when the 32-byte receive FIFO becomes full.
Differences Between the UNIT-mode and Sequential-mode Receptions
The receive FIFO is disabled in UNIT mode. Writing a 1 to the SPICT<RXE> bit initiates
In this mode, the RFUL and REND interrupts are generated when the receive data is
The Sequential-mode reception automatically receives the data as long as the receive
Received data is stored into the receive FIFO by writing a 1 to the SPICT<RXE> bit.
This mode of receptionkeeps receiving the next data automatically unless the data
Writing a 0 to the SPICT<RXE> bit during a receptionstops the data reception after
The RFUL interrupt is generated when the size of data stored into the FIFO reaches 16
The UNIT-mode reception receives only one UNIT-size data. The UNIT mode for the
92CF26A-491
TMP92CF26A
2009-06-25