TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 494

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

Note: If the data transmission and reception are not performed simultaneously, data communication should be
must be set to 1.
into standby mode for the UNIT-mode reception. Writing a 1 to the SPICT<RXE> bit after
writing a 1 to the <FDPXE> bit does not immediately initiate the receive operation. This is
because the data to be transmitted at the same time has not been prepared. Transmit and
receive operation is started only after the transmit data is written into the SPITD register
where SPICT<TXE> = 1.
simultaneous transmit and receive operation.:
Receiver
Transmitter
Transmit and Receive Operation
When performing a data transmissionand reception simultaneously, the FDPXE bit
Write a 1 to the SPICT<RXE> bit after writing a 1 to the FDPXE bit to put the receiver
The figure below shows the operations of the receiver and transmitter for the
SPCLK output
SPCLK output
SPDI input
SPDO output
performed with the FDPXE bit cleared to 0.
receiving
Figure 3.17.8 Transmit and Receive Operation
Start
92CF26A-492
transmitting
Start
Bit 0
LSB
LSB
Bit 1
Bit 1
Bit 2
Bit 2
Bit 3
Bit 3
Bit 4
Bit 4
Bit 5
Bit 5 Bit 6
Bit 6
TMP92CF26A
Bit 7
2009-06-25