TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 50

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

Note: The values to be set in the I/O registers for UART and USB are not described here. If these functions are
(2) I/O register settings
needed in a user program, set each I/O register as necessary.
without a reset being asserted, the settings of these I/O registers must be taken into
account. Also note that the registers in the CPU and the internal RAM remain in the
state after execution of the boot program.
WDMOD
WDCR
SYSCR0
SYSCR1
SYSCR2
PLLCR0
PLLCR1
INTEUSB
INTETC01
Table 3.4.5 shows the I/O registers that are set by the boot program.
After the boot sequence, if execution moves to an application system program
Register
Name
Table 3.4.5 I/O Register Settings by Boot Program
Set Value
2CH
B1H
70H
00H
60H
00H
00H
00H
04H
44H
or
Watchdog timer not active
Watchdog timer disabled
High-frequency and low-frequency oscillators operating
Clock gear = 1/1
Initial value
PLL clock not used
Normally PLL is disabled.
However, only in the case of booting via USB, PLL is
activated for USB.
USB interrupt level setting
INTTC interrupt level setting
92CF26A-48
Description
TMP92CF26A
2009-06-25