TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 506

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

Note: In case of I
(a) <SYSCKEn>
(b) <DTFMTn1:n0>
(c) <BITn>
(d) <DIRn>
(e) <CNTEn>
(f) <TXEn>
(h) <EDGEn>
(g) <CLKEn>
<CLKEn>= “1” with I
with I
operating, for reduce the power consumption, we recommends to disable:
<SYSCKEn>= “0”.
the data format, set <SYSCKEn>= “1”, <CNTEn>=“0” and <TXEn>= “0”.
the data format, set <SYSCKEn>= “1”, <CNTEn>= “0” and <TXEn>= “0”.
the data format, set <SYSCKEn>= “1”, <CNTEn>=“0” and <TXEn>=“0”.
Clock generator counter will not clear by <TXEn>=“0” and <CNTEn>=“1”
Transmission is stopped by <TXEn>=“0”, started by <TXEn>=“1”.
during effective data out period.
the rising edge of clock.
falling edge of clock.
data format, set <SYSCKEn>=“1”, <CNTEn>=“0” and <TXEn>=“0”.
This bit controls to connect source clock to I
In case of this circuit is operated, it must enable: <SYSCKEn>= “1”. And except
This bit controls data format: I
It is not possible to change data format during data transmission. Before changing
This bit controls data length: 8/16 bits.
It is not possible to change data length during data transmission. Before changing
This bit controls direction: LSB_Fast or MSB_Fast
It is not possible to change data direction during data transmission. Before changing
This bit controls clock generator counter: Clear/Start.
Clock generator counter will clear by <TXEn>=“0” and <CNTEn>=“0”, However,
This bit controls data transmission and Fi/Fo buffer clear: Trans/Stop and Clear
Output Fi/Fo buffer is cleared by <TXEn>=“0”.
This bit controls CLK out period.
<CLKEn>=“0”: always out I2SnCKO clock, <CLKEn>=“1”: I2SnCKO clock out
This bit controls relation of phase between I2SnCKO and data.
<EDGEn>=“0”: the data is changed in the falling of clock, and the data is latched in
<EDGEn>=“1”: the data is changed in the rising of clock, and the data is latched the
It is not possible to change phase during data transmission. Before changing the
2
S format.
2
S format, firstly I2SnWS signal change and after 1clock period, effective data out. If set to
2
S format, 1 clock pulse after I2SnWS don't out. It is not possible <CLKEn>=“0” setting
92CF26A-504
2
S, right justify and left justify.
2
S circuit.
TMP92CF26A
2009-06-25