TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 507

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

(i) <WLVLn>
(j) <TEMPn>
(k) <FSELn>
(l) <CLKSn>
(m) <CKn7:n0>
(n) <WSn5:n0>
<WLVLn>. Refer the “Fi/Fo buffer and data format" in details.
Before changing the data format, set <SYSCKEn>= “1”, <CNTEn>= “0” and
<TXEn>=“0”.
in details.
the data format, set <SYSCKEn>=“1”, <CNTEn>=“0” and <TXEn>=“0”.
time. In details, refer the chapter of PLL, please.
changing the counter value, set <SYSCKEn>=“1”, <CNTEn>=“0” and <TXEn>=“0”.
changing the counter value, set <SYSCKEn>=“1”, <CNTEn>=“0” and <TXEn>=“0”.
This bit controls phase of Word Select signal: I2SnWS
I2SnWS signal always out “1” level first. The order of data output changes by
It is not possible to change phase of Word Select signal during data transmission.
This bit is empty flag of output Fi/Fo buffer.
<TEMPn>=“1”: Fi/Fo buffer is empty, <TEMPn>=“0”: remain data in Fi/Fo buffer.
This bit is read only. Fi/Fo buffer is cleared by <TXEn>=“0”
This bit controls sound mode: Stereo / Monaural
<FSELn>=“0”: Stereo, <FSELn>=“1”: Monaural. Refer the chapter of “Data format”
It is not possible to change sound mode during data transmission. Before changing
This bit controls source clock to I
<CLKSn>=“0”: f
In case of using f
These bits are set counter value of clock generator. [I2SnCK]
It is not possible to change these counter value during data transmission. Before
These bits are set counter value of clock generator. [I2SnWS]
It is not possible to change these counter value during data transmission. Before
SYS
PLL
is supplied, <CLKSn>=“1”: f
, before set f
92CF26A-505
2
S circuit: f
PLL
clock, please take care set -up time: Lock-Up
SYS
/ f
PLL
PLL
is supplied.
.
TMP92CF26A
2009-06-25