TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 508

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

3.18.3
Description of Operation
(1) Settings the transfer clock generator and Word Select signal
(2) Data format
generated using the system clock (f
a prescaler and a dedicated clock generator to set the transfer clock and sampling
frequency.
cleared by setting <CNTEn> to “0”.
I2SnCTL<DTFMTn1:n0> register. And support stereo and monaural both, controlled
by I2SnCTL<FSELn> register.
A) Clock generator
B) Word Select
In the I
The counters are started by setting I2SnCTL<CNTEn> to “1” and are stopped and
This circuit support I
•
•
•
clock selected by I2SnCTL<CLKSn>.
I2SnCKO signal.
whether left data or right data is being transmitted in the I
signal is clocked out in synchronization with the data transfer clock. In only
channel 0, this signal can be used as an AD conversion trigger signal for the
ADC. How valid data is to be output in relation to the WS signal can be
specified as I
interrupt request can be output to the ADC on the rising edge of the WS signal.
(This is controlled by the ADC’s control register.)
8-bit counter
6-bit counter
Word Select signal (I2SnWS)
2
S unit, the clock frequencies for the I2SnCKO and I2SnWS signals are
This is an 8-bit counter that generates the I2SnCKO signal by dividing the
This is a 6-bit counter that generates the I2SnWS signal by dividing the
The I2SnWS signal is used to distinguish the position of valid data and
2
S format, left-justified, or right-justified. In only channel 0, an
2
S format, left justify and right justify format by setting
92CF26A-506
SYS
) as a source clock. The system clock is divided by
2
TMP92CF26A
S format. This
2009-06-25