TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 519

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

Display colors
Number of pixels that can be
displayed
Data rotation function
PIP function support
Source data bus width
(SRAM, SDRAM)
Destination data bus width
(LCD driver)
Maximum transfer rate
(VRAM read)
3.19.1
LCD driver data bus:
LD23 to LD0 pins
LCP0 pin
LHSYNC pin
LLOAD pin
LGOE0 to LGOE2
pins
LFR pin
LVSYNC pin
LDIV pin
LCD Driver
LCDC Features according to LCD Driver Type
(This table assumes the connection with a TOSHIBA-made LCD driver.)
Table 3.19.1 LCDC Features according to LCD Driver Type
256/4096/65536/262144/16777216 colors
For 4096 colors or less
Rows (Commons):
64, 96, 128, 160, 200, 240, 320, 480
Columns (Segments):
64, 128, 160, 240, 320, 480, 640
For 65536 colors or less
Rows (Commons):
64, 96, 128, 160, 200, 240, 320, 480
Columns (Segments):
64, 128, 160, 240, 320, 480
16777216 colors or less
ROW(common):
64,96,128,160,200,240,320,480
Column (Segment):
64,128,160,240,320
Horizontal flip, vertical flip, horizontal and vertical flip, 90-degree rotation
(supported for QVGA size, 65536 colors only)
A sub window can be inserted.
16 bits (32 bits: internal RAM)
8 to 24 bits
1-clk / 4byte at internal RAM
To be connected to LCD driver data bus.
・ 8-bit mode: LD7 to LD0
・TFT mode: LD23 to LD0
Data shift clock for TFT source driver
Vertical shift clock for TFT gate driver
Enable signal for TFT source driver to load data
to TFT panel
Adjustment signal for TFT gate driver’s gate
control signal
LCD alternate signal output pin. To be
connected to column/row driver’s FR pin.
This signal indicates the start of shift clock
capture by TFT gate driver.
This signal indicates the inversion of data. To be
connected to TFT source driver having the data
inversion function.
TFT
92CF26A-517
Shift Register Type
Monochrome, 4/16/64 grayscale levels
256/4096/65536 colors
For Monochrome/grayscale/4096 colors or less
Rows (Commons):
64, 96, 120, 128, 160, 200, 240, 320, 480
Columns (Segments):
64, 120, 128, 160, 240, 320, 480, 640
For 65536 colors or less
Rows (Commons):
64, 96, 128, 160, 200, 240, 320, 480
Columns (Segments):
64, 128, 160, 240, 320
−
16 bits (32 bits: internal RAM)
8 bits
Shift clock pulse output pin 0. To be connected to
column driver’s CP pin. The LCD driver latches the
data bus value on the falling edge of this pin.
Latch pulse output pin. To be connected to the LCD
driver’s LP pin. The display data in the LCD driver’s
output line register is updated on the rising edge of
this pin.
N/A
N/A
LCD alternate signal output pin. To be connected to
column/row driver’s FR pin.
Frequency that sets LCD refresh rate
N/A
STN
TMP92CF26A
2009-06-25