TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 524

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TMP92xy26AXBG

Manufacturer Part Number
TMP92xy26AXBG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP92xy26AXBG

Package
FPGA228
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
144/288
Architecture
32-bit CISC
Usb/spi Channels
1/1
Uart/sio Channels
2
I2c/sio Bus Channels
1
(s)dram Controller
1
Adc 10-bit Channel
6
Da Converter
-
Timer 8-bit Channel
8
Timer 16-bit Channel
2
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
Y
Number Of I/o Ports
136
Power Supply Voltage(v)
3.0 to 3.6
LCDHO2W
(0298H)
LCDHO1W
(0297H)
LCDHO0W
(0296H)
LCDHWB8
(0299H)
LCDHSW
(0294H)
LCDLDW
(0295H)
bit Symbol
Read/Write
Reset State
Function
bit Symbol
Read/Write
Reset State
Function
bit Symbol
Read/Write
Reset State
Function
bit Symbol
Read/Write
Reset State
Function
bit Symbol
Read/Write
Reset State
Function
bit Symbol
Read/Write
Reset State
Function
LGOE2 width (bits 9-8) LGOE1 width (bits 9-8)
HSW7
LDW7
O0W7
O1W7
O2W7
O2W9
7
0
7
0
7
0
7
0
7
0
7
0
HSW6
O0W6
O1W6
O2W6
LDW6
O2W8
6
6
6
6
6
0
0
0
0
0
6
0
signal width Bit8,9 Register
LHSYNC width Register
LLOAD width Register
LGOE0 width Register
LGOE1 width Register
LGOE2 width Register
92CF26A-522
HSW5
O0W5
O1W5
O2W5
O1W9
LDW5
5
5
5
5
5
5
0
0
0
0
0
0
LHSYNC width (bits 7-0)
LLOAD width (bits 7-0)
LGOE0 width (bits 7-0)
LGOE1 width (bits 7-0)
LGOE2 width (bits 7-0)
HSW4
LDW4
O0W4
O1W4
O2W4
O1W8
4
0
4
0
4
0
4
0
4
0
4
0
W
W
W
W
W
W
width (bit 8)
LGOE0
HSW3
O0W3
O1W3
O2W3
LDW3
O0W8
3
3
3
3
3
0
0
0
0
0
3
0
LLOAD width (bits 9-8)
HSW2
O0W2
O1W2
O2W2
LDW2
LDW9
2
2
2
2
2
0
0
0
0
0
2
0
HSW1
LDW1
O0W1
O1W1
O2W1
LDW8
1
0
1
0
1
0
1
0
1
0
1
0
TMP92CF26A
width (bit 8)
2009-06-25
LHSYNC
HSW0
O0W0
O1W0
O2W0
LDW0
HSW8
0
0
0
0
0
0
0
0
0
0
0
0

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