TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 527

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

3.19.3
3.19.3.1 Outline
3.19.3.2 Display Memory Mapping
Note: While display RAM data is being read, the CPU operation is halted by the internal BUSREQ signal. Therefore,
Description of Operation
the CPU stop time must be taken into account in programming.
address, color mode, and LCD size are specified, the start register is set to start the
LCDC operation.
reads data of the display size from the display RAM, stores the data in the FIFO buffer
in the LCDC, and then returns the bus to the CPU.
bus (LD pin). At this time, control pins (such as LCP0) that are connected to the LCD
driver also output specified waveforms in synchronization with the transfer of display
data.
RAM. Since the internal RAM allows very fast accesses (32-bit bus, 2-1-1-1 read/write),
it enables data transfer to the LCD driver (DMA operation) with the minimum CPU
stop time. Using the internal RAM also greatly reduces power consumption during
LCD display.
size depending on the selected color mode, the required display RAM size also varies
with each color mode. (The color mode can be selected from a range of monochrome to
16777216 colors.)
RAM data. Likewise, the number of display RAM data used for displaying one pixel in
each color mode is as follows:
19200 bytes of display RAM space (320 × 240 × 2 = 152600 bits = 19200 bytes).
later in this chapter.
After the required settings such as the operation mode, display data memory
The LCDC issues a bus request to the CPU. When the bus is granted, the LCDC
The display data in the FIFO buffer is transferred to the LCD driver via a dedicated
External SDRAM, SRAM, or internal RAM (144 Kbytes) can be used as the display
Since the number of bits needed to display one pixel varies even for the same display
In monochrome mode, one pixel of display data corresponds to one bit of display
For example, a 320-segment × 240-common display in 4-grayscale mode requires
For details, refer to “Memory Map Image and Data Output in Each Display Mode”
4-grayscale 1 pixel = 2 bits
16-grayscale 1 pixel = 4 bits
64-grayscale
STN 256-color
STN 4096-color
STN 65536-color
TFT 256K-color
TFT 16M-color
92CF26A-525
1 pixel = 6 bits
1 pixel = 8 bits
1 pixel = 12 bits
1 pixel = 16 bits
1 pixel = 16 bits (not 18 bits)
1 pixel = 24 bits
TMP92CF26A
2009-06-25