TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 529

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

Signal Name
LCP0 signal
(Only at valid data output)
(Always output)
LFR signal (FREDGE=0)
(Frame divide control)
(Line)
(Dot)
LLOAD signal
LD23-LD0 signal
LDINV signal
LLOAD signal details
LFR signal (FREDGE=1)
LVSYNC signal
(Enable width control)
(Phase control)
DLS=0 (Line inversion)
LHSYNC signal
LLOAD signal
LGOEn signal
(Enable width control)
(Phase control)
(Delay control)
3.19.3.4 Basic Operation
LCDC and adjustable elements. The adjustable elements for each signal include
enable time, phase, and delay time.
(STN/TFT) and specifications to be used.
The following diagram shows the basic timings of the waveforms generated by the
The signals used and their connections and settings vary with the LCD driver type
(Enable width control)
(Enable width control)
(Delay control)
(Line divide)
(Line divide)
(Phase control)
(Valid data output)
92CF26A-527
(Phase control)
(Phase control)
Frame period (Refresh rate)
(Dot divide)
(Dot divide)
TMP92CF26A
2009-06-25