TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 530

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

Internal signal (f
LD23-LD0
LD23-LD0
LD23-LD0
3.19.3.5 Reference Clock LCP0
LCP0
LCP0
LCP0
SYS
Minimum speed
Maximum speed
)
STN and setting LCDMODE0<SCPW1:0> and LCDMODE1<SWPW2>. The clock
speed should be selected to meet the characteristics of the LCD driver to be used.
and f
STN monochrome/grayscale
STN color
TFT
LCP0 is used as the reference clock for all the signals in the LCDC.
This section explains how to set the frequency (period) of the LCP0 signal.
The LCP0 clock speed (LD bus transfer speed) is determined by selecting TFT or
The LCP0 period can be selected from four types: f
overlapping the current line signal.
data cannot be transferred properly. Set the data transfer speed so that each
transfer completes within the LHSYNC period.
cannot be prepared in time, causing wrong data to be transferred. The maximum
transfer speed is limited by the operation mode and display RAM type (bus width,
wait condition, and so on). If the data rotation function is used, the transfer speed
must be slower.
SYS
The LCP0 period needs to be short enough to prevent the next line signal from
The transfer speed of display data must be set to suit the refresh rate; otherwise
If the LCP0 period is too short, the data to be transferred to the LCD driver
/48.
Figure 3.19.1 LCP Frequency Selection
:
:
:
92CF26A-528
Segment size / 8 × LCP0 [s: period] < LHSYNC [s: period] STN color
Segment size × 3 / 8 LCP0 [s: period] < LHSYNC [s: period]
Segment size × LCP0 [s: period] < LHSYNC [s: period]
SYS
/2, f
SYS
/4, f
SYS
/8, f
f
f
f
SYS
SYS
SYS
TMP92CF26A
SYS
/48
/2
/4
2009-06-25
/16, f
SYS
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