TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 537

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TMP92xy26AXBG

Manufacturer Part Number
TMP92xy26AXBG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP92xy26AXBG

Package
FPGA228
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
144/288
Architecture
32-bit CISC
Usb/spi Channels
1/1
Uart/sio Channels
2
I2c/sio Bus Channels
1
(s)dram Controller
1
Adc 10-bit Channel
6
Da Converter
-
Timer 8-bit Channel
8
Timer 16-bit Channel
2
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
Y
Number Of I/o Ports
136
Power Supply Voltage(v)
3.0 to 3.6
LCDLDDLY
(0290H)
Note 1: The back dummy LCP0 (horizontal back porch) must have a minimum of two LCP0 clocks.
Note 2: The delay time that is set in LCDLDDLY<LDD6:0> is counted based on LHSYNC (with 0 delay).
Example 1) Setting the refresh rate to 200 Hz under the following conditions:
bit Symbol
Read/Write
Reset State
Function
• Setting method
the total of LHSYNC period in the LVSYNC period is defined by the value set in
LCDPRVSP<PLV6:0>.
total number of LCP0 clocks in the LHSYNC period is defined by the value set in
LCDLDDLY<LDD6:0>.
The front dummy LHSYNC (vertical front porch) not accompanied by valid data in
Front dummy LHSYNC (vertical front porch) = <PLV6:0>
The back dummy LHSYNC (vertical back porch) is defined as follows:
(<LVP9:0>+1) − (valid LHSYNC: common size) − (front dummy LHSYNC: <PLV6:0>)
The vertical back porch must have a minimum of one dummy clock.
The front dummy LCP0 (horizontal front porch) not accompanied by valid data in the
Front dummy LCP0 (horizontal front porch) = <LDD6:0>
The back dummy LCP0 (horizontal back porch) is defined as follows:
(<LH15:0> + 1) − (Valid LCP0: segment size) − (Front dummy LCP0: <LDD6:0>)
f
LCDMODE0<SCPW1:0> = 00
Internal reference clock LCP0 = f
Therefore, LCP0 period = 1 / 7.5 [MHz] = 0.133 [μS]
When <LVP9:0> = 239 (minimum value):
SYS
LVSYNC [S: period]
5 [mS]
LH + 1
Condition 1:
Condition 2:
Condition 3:
Data output
0: Sync with
1: 1 clock
timing
LLOAD
later than
LLOAD
= 30 MHz, STN mode, 320-segment × 240-common, 4096-color display,
PDT
R/W
7
0
Refresh rate = 200 Hz, Refresh cycle = 5 [ms]
LH = <LH15:0> ≥ (320×3/8) − 1 = 119
LV = <LVP9:0> ≥ 240 − 1
LDD6
6
0
=
=
=
=
=
LLOAD Delay Register
LHSYNC [S: period] × ((LV9:0) + 1 )
LCP0 [S: period] × ((LH15:0 ) + 1 ) × ((LV9:0) + 1 )
( 1 / 7.5 [MHz]) × ( LH + 1) × 240
( 5 × 10
156.25
92CF26A-535
LDD5
SYS
5
0
/ 4 = 30 [MHz] / 4 = 7.5 [MHz]
-3
) × ( 7.5 × 10
LDD4
4
0
LLOAD delay (bits 6-0)
6
) / 240
LDD3
W
3
0
LDD2
2
0
LDD1
1
0
TMP92CF26A
2009-06-25
LDD0
0
0

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