TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 539

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

LCDVSP
(028CH)
(028DH)
LCDCTL1
(0286H)
(1) LVSYNC Signal
LVSP=1
LVSP=0
bit Symbol
Read/Write
Reset State
Function
bit Symbol
Read/Write
Reset State
Function
bit Symbol
Read/Write
Reset State
Function
screen update (refresh rate). The LVSYNC period is defined as an integral multiple of the
period of the horizontal synchronization signal LHSYNC.
the LHSYNC period. The value to be set in LCDVSP<LV9:0> should be “common size +
number of dummy clocks” or larger for TFT and STN.
The period of the vertical synchronization signal LVSYNC indicates the time for each
The LVSYNC period is calculated as the product of the value set in LCDVSP<LV 9:0> and
LVSYNC [s: period] = LHSYNC [s: period] × (<LVP9:0> + 1)
clocks of LHSYNC in LCDCTL1<LVSW1:0>.
<LVSP>.
The enable width of the LVSYNC signal can be specified as 1 clock, 2 clocks, or 3
The phase of the LVSYNC signal can be inverted by the setting of LCDCTL1
LCP0
phase
0: Rising
1: Falling
LVP7
LCP0P
(Enable width control)
7
7
0
7
1
LHSYNC
phase
0: Rising
1: Falling
LVP6
= LCP0 [s: period] × (<LH15:0> + 1) × (<LVP9:0> + 1)
LHSP
6
6
0
LCD LVSYNC Pulse Register
6
0
LCD Control 1 Register
R/W
92CF26A-537
LVSYNC
phase
0: Rising
1: Falling
LVP5
5
5
0
LVSP
(Phase control)
5
1
Refresh rate
LVSYNC period (bits 7-0)
LVSYNC signal
LLOAD
phase
0: Rising
1: Falling
LVP4
4
4
0
LLDP
4
0
W
LVP3
3
3
0
3
LVP2
2
2
0
2
LVSYNC
enable time control
00: 1 clock of LHSYNC
01: 2 clocks of LHSYNC
10: 3 clocks of LHSYNC
11: Reserved
LVP1
LVP9
LVSYNC period
LVSW1
1
1
0
0
1
0
(bits 9-8)
TMP92CF26A
W
R/W
2009-06-25
LVP0
LVP8
LVSW0
0
0
0
0
0
0