TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 542

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

LCDHSDLY
(028FH)
LCDCTL1
(0286H)
LHSP=0
LHSP=1
bit Symbol
Read/Write
Reset State
Function
bit Symbol
Read/Write
Reset State
Function
inserted in the LHSYNC signal.
As shown in the diagram below, delay time of 0 to 127 pulses of the LCP0 clock can be
Delay time = <HSD6:0>
The phase of the LHSYNC signal can be inverted by the setting of LCDCTL1 <LVSP>.
Signal Name
LCP0 signal
LVSYNC signal
Reference LHSYNC
(with 0 delay)
LHSYNC signal
Delay control 1
(Enable width control)
LCP0
phase
0: Rising
1: Falling
LHSYNC period
LCP0P
7
7
1
LHSYNC
phase
0: Rising
1: Falling
HSD6
LHSP
6
0
6
0
LHSYNC Delay Register
LCD Control 1 Register
R/W
(Phase control)
92CF26A-540
LVSYNC
phase
0: Rising
1: Falling
HSD5
5
0
LVSP
5
1
LHSYNC signal
LLOAD
phase
0: Rising
1: Falling
HSD4
4
0
LLDP
LHSYNC delay (bits 6-0)
4
0
HSD3
W
3
0
3
HSD2
2
0
2
LVSYNC
enable time control
00: 1 clock of LHSYNC
01: 2 clocks of LHSYNC
10: 3 clocks of LHSYNC
11: Reserved
HSD1
LVSW1
1
0
1
0
TMP92CF26A
R/W
2009-06-25
HSD0
LVSW0
0
0
0
0