TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 545

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TMP92xy26AXBG

Manufacturer Part Number
TMP92xy26AXBG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP92xy26AXBG

Package
FPGA228
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
144/288
Architecture
32-bit CISC
Usb/spi Channels
1/1
Uart/sio Channels
2
I2c/sio Bus Channels
1
(s)dram Controller
1
Adc 10-bit Channel
6
Da Converter
-
Timer 8-bit Channel
8
Timer 16-bit Channel
2
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
Y
Number Of I/o Ports
136
Power Supply Voltage(v)
3.0 to 3.6
LCDHWB8
(0299H)
LCDLDW
(0295H)
LCP0
LD23-LD0
LLOAD
LLOAD
LCDLDDLY<PDT> = 1
bit Symbol
Read/Write
Reset State
Function
bit Symbol
Read/Write
Reset State
Function
LCDLDDLY<PDT> = 0
set in a range of 0 to 1024 pulses of the LCP0 clock.
shown below.
The enable width of the LLOAD signal is specified using LCDLDW<LDW9:0>. It can be
The actual enable width is determined depending on the LCDLDDLY<PDT> setting, as
Enable width = <LDW9:0> + 1
Enable width = <LDW9:0>
When LCDCTL0<LCP0OC>=1, the enable width of the LLOAD signal is shown below.
LGOE2 width (bits 9-8) LGOE1 width (bits 9-8)
LDW7
O2W9
7
7
0
0
LDW6
O2W8
6
0
6
0
Signal width Bit8,9 Register
LLOAD width Register
92CF26A-543
O1W9
LDW5
(when <PDT> = 0)
5
5
0
0
LLOAD width (bits 7-0)
LDW4
O1W8
(when <PDT> = 1, <LDW9:0>=0 is prohibited)
4
4
0
0
W
W
width (bit 8)
LGOE0
LDW3
O0W8
3
3
0
0
LLOAD width (bits 9-8)
LDW9
LDW2
2
2
0
0
LDW1
LDW8
1
1
0
0
TMP92CF26A
2009-06-25
width (bit 8)
LHSYNC
HSW8
LDW0
0
0
0
0

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