TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 550

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

LVSYNC
LFR
<FREDGE>=1
<FRMON> = 0
LFR
<FREDGE>=1
<FRMON>= 1
<FMP7:0> = N
<FML7:0> = any
<DLS> = 0
LFR
<FREDGE>=0
<FRMON> = 0
LHSYNC
LFR
<FREDGE>=0
<FRMON>= 1
<FMP7:0> = N
<FML7:0> = any
<DLS> = 0
(5) LFR Signal
Note1: The effect of this function varies with the characteristics of the LCD driver and LCD panel to be used.
Note2: LFR signal delaies synchronous with LHSYNC signal.
Generally, setting a prime number (3, 5, 7, 11, 13 and so on) as the “N” value produces better results.
liquid crystal cells. With small screens in monochrome mode, the polarity of the LFR signal
is normally inverted in synchronization with each screen display. With large screens or
when grayscale or color mode is used, the polarity is inverted at shorter intervals to adjust
the display quality.
at intervals of “LHSYNC x N” (LHSYNC: internal reference signal with 0 delays). The “N”
value is specified in LCDDVM0<FML3:0> and LCDDVM1<FML7:4>.
LHSYNC signal, and when <DLS>="0" and <FREDGE>=1, LFR signal synchronous with
rear edge of LHSYNC signal.
signal is inverted in synchronization with the LVSYNC period.
(The refresh rate is not changed.)
The LFR (frame) signal is used to control the direction of bias the LCD driver applies on
When LCDCTL0<FRMON>=“1” and LCDCTL0<DLS> = “0”, the LFR signal is inverted
When <DLS>= “0” and <FREDGE>= “0”, LFR signal synchronous with front edge of
When LCDCTL0<FRMON> is set to “0” to disable the frame divide function, the LFR
Enabling this function does not affect the waveform and timing of the LVSYNC signal.
N
N
92CF26A-548
TMP92CF26A
2009-06-25