TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 552

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TMP92xy26AXBG

Manufacturer Part Number
TMP92xy26AXBG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP92xy26AXBG

Package
FPGA228
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
144/288
Architecture
32-bit CISC
Usb/spi Channels
1/1
Uart/sio Channels
2
I2c/sio Bus Channels
1
(s)dram Controller
1
Adc 10-bit Channel
6
Da Converter
-
Timer 8-bit Channel
8
Timer 16-bit Channel
2
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
Y
Number Of I/o Ports
136
Power Supply Voltage(v)
3.0 to 3.6
LCDDVM1
(0288H)
LCDCTL0
(0285H)
LCDDVM0
(0283H)
Note: When select STN mode, LCP0 is output at valid data only regardless of the setting of <LCP0OC> bit.
bit Symbol
Read/Write
Reset State
Function
bit Symbol
Read/Write
Reset State
Function
bit Symbol
Read/Write
Reset State
Function
PIP
function
0:Disable
1:Enable
FMP3
FMP7
PIPE
7
7
0
0
7
0
Segment
data
0: Normal
1: Always
output “0”
LCP0 DVM (bits 3-0)
LCP0 DVM (bits 7-4)
FMP2
FMP6
6
6
R/W
0
0
ALL0
0
6
LCD Control 0 Register
Divide FRM 0 Register
Divide FRM 1 Register
92CF26A-550
Frame
divide
setting
0: Disable
1: Enable
FMP1
FMP5
FRMON
5
5
0
0
0
5
Always
write “0”
FMP0
FMP4
4
4
0
0
R/W
4
0
R/W
R/W
FML3
FML7
3
3
0
0
3
LHSYNC DVM (bits 3-0)
LHSYNC DVM (bit 7-4)
FR signal
LCP0/Line
selection
0:Line
1:LCP0
FML2
FML6
2
2
0
0
DLS
2
0
LCP0(Note
0: Always
1: At valid
LLOAD
0: At setting
1: At valid
FML1
FML5
width
LCP0OC
output
data only
in register
data only
1
1
0
0
R/W
1
0
TMP92CF26A
2009-06-25
FML0
FML4
LCDC
operation
0: Stop
1: Start
START
0
0
0
0
0
0

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