TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 554

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

STN monochrome (1-pixel display data = 1-bit memory data)
Display Memory
LD Bus Output
8-bit type
LD0
LD1
LD2
LD3
LD4
LD5
LD6
LD7
STN 4-grayscale (1-pixel display data = 2-bit memory data)
Display Memory
LD Bus Output
8-bit type
LD0
LD1
LD2
LD3
LD4
LD5
LD6
LD7
LSB
D0
LSB
D0
0
0
0
1
2
3
4
5
6
7
1
1
1 - 0
3 - 2
5 - 4
7- 6
9- 8
11-10
13-12
15-14
Figure 3.19.2 Memory Map Image and Data Output in STN Monochrome/4-Grayscale Mode
→ 8 …
→ 9 …
→ 10 …
→ 11 …
→ 12 …
→ 13 …
→ 14 …
→ 15 …
2 3
2 3
•
Address 0
Address 0
Note: When setting 240 segment, 256 segment size of data is required.
→ 17-16 …
→ 19-18 …
→ 21-20 …
→ 23-22 …
→ 25-24 …
→ 27-26 …
→ 29-28 …
→ 31-30 …
4 5 6
4 5 6
Memory Map Image and Data Output in Each Display Mode
7
7
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Address 1
Address 1
92CF26A-552
Address 2
Address 2
Address 3
Address 3
MSB
MSB
TMP92CF26A
D31
D31
2009-06-25