TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 565

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

LCDMODE1<INTMODE>=0
LCDMODE1<INTMODE>=1
LVSYNC
LHSYNC
LLOAD
D15-0(VRAM Read)
Interrupt request
Interrupt request
LCDMODE1
(0281H)
3.19.4
Note: The interrupt request generates when reading the data from VRAM at once. Since reading from VRAM is
Note: The LCDMODE1<INTMODE> setting must not be changed while the LCDC is operating. Be sure to set
bit Symbol
Read/Write
Reset State
Function
synchronous with the LLOAD signal that is output immediately after the LVSYNC signal.
each VRAM read before the LLOAD generates (once in each LLOAD period).
VRAM read before the first LLOAD generates (once in each LVSYNC period).
Interrupt Function
The LCDC has two types of interrupts.
One is generated synchronous with the LLOAD signal and the other is generated
LCDMODE1<INTMODE> is used to switch between these two types of interrupts.
When LCDMODE1<INTMODE>=0, an interrupt request is generated at the start of
When LCDMODE1<INTMODE>=1, an interrupt request is generated at the start of
executed by DMA with bus request to the CPU, DMA operation is given priority. Thus CPU accepts interrupt
immediately after reading the data from VRAM.
LCDCTL0<START> to “0” to stop the LCDC operation before changing the interrupt setting.
Data rotation function
(Supported for 64K-color: 16bps
only)
000: Normal
001: Horizontal flip 101: Reserved
010: Vertical flip
011: Horizontal & vertical flip
111: Reserved
LDC2
7
0
LDC1
6
0
100: 90-degree
110: Reserved
LCDMODE1 Register
92CF26A-563
LDC0
5
0
R/W
LD bus
inversion
0: Normal
1: Invert
LDINV
4
0
Auto bus
inversion
0: Disable
1: Enable
(Valid only
for TFT)
AUTOINV
3
0
Interrupt
selection
0:LLOAD
1:LVSYNC
INTMODE
2
0
LFR edge
0: LHSYNC
1:LHSYNCR
FREDGE
Front
Edge
EAR Edge
1
0
TMP92CF26A
W
2009-06-25
LD bus
Trance
Speed
0: normal
1: 1/3
SCPW2
0
0