TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 573

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

LCDMODE1
(0281H)
3.
function.
display RAM start address of main/sub area should be set differently from when in normal
mode, as shown in the table below.
Note: The <LDC2:0> setting must not be changed while the LCDC is operating. Be sure to set LCDCTL0<START>
bit Symbol
Read/Write
Reset State
Function
The <LDC2:0> bits in the LCDMODE1 register are used to set the display data rotation
When the horizontal and vertical flip function or 90-degree rotation function is used, the
Setting Method
to “0” to stop the LCDC operation before changing <LDC2:0>.
How to calculate the point B address:
(320×240×16/8) −2
Normal
90-degree rotation
Horizontal flip
Vertical flip
Horizontal and vertical flip
Data rotation function
(Supported for 64K-color: 16bps
only)
000: Normal
001: Horizontal flip 101: Reserved
010: Vertical flip
011: Horizontal & vertical flip
111: Reserved
LDC2
7
0
Mode
LDC1
Display RAM Image (QVGA 320 × 240)
6
0
100: 90-degree
110: Reserved
LCDMODE1 Register
Point A
Point B
Point B
92CF26A-571
Point A
Point B
Point A
LDC0
Setting Point
= 153600−2
= 153598 [decimal]
= 257FE [hex]
5
0
R/W
LD bus
inversion
0: Normal
1: Invert
LDINV
4
0
Display RAM Start Address
00000h
257FEh
00000h
257FEh
257FEh
Point B
Auto bus
inversion
0: Disable
1: Enable
(Valid only
for TFT)
AUTOINV
Setting Example
3
0
Interrupt
selection
0:LLOAD
1:LVSYNC
INTMODE
2
0
LFR edge
0: LHSYNC
1:LHSYNCR
FREDGE
Front
Edge
EAR Edge
1
0
TMP92CF26A
W
2009-06-25
LD bus
Trance
Speed
0: normal
1: 1/3
SCPW2
0
0