TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 574

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

3.19.5.3 Considerations for Using the LCDC
1.
2.
3.
If the operation mode is changed while the LCDC is operating, a maximum of one
frame may not be displayed properly. Although this degree of disturbance does not
normally pose any problem (e.g. no response on LCD, display not visible to human
eyes), the actual operation largely depends on the conditions such as the LCD
driver, LCD panel, and frame frequency to be used. It is therefore recommended
that operation checks be performed under the actual conditions.
The LCDMODE1<LDC2:0> setting must not be changed while the LCDC is
operating. Be sure to set LCDCTL0<START> to “0” to stop the LCDC operation
before changing <LDC2:0>.
The LCDC obtains the bus from the CPU when it has some operation to perform.
Since the TMP92CF26A includes other units that act as bus masters such as
HDMA and SDRAMC, it is necessary to estimate the bus occupancy rate of each
bus master in advance. For details, see the chapter on HDMA.
92CF26A-572
TMP92CF26A
2009-06-25