TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 579

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

LCDLDDLY<PDT> = 1
LLOAD
LGOE0
LCP0
LD17-LD0
LD17-LD0
LVSYNC
LHSYNC
LHSYNC
LLOAD
LGOE0
TFT-3(TFT panel: 320com x 240seg by TM company) (f
ld
ld
ld
ld
ld
ld
ld
ld
ldw
ldw
ld
ld
ld
ld
ld
ld
ld
ld
ldl
set
(lcdmode0),7dh
(lcdmode1),00h
(lcdsize),84h
(lcdctl0),20h
(lcdctl1),0e0h
(lcdctl2),00h
(lcddvm0),01h
(lcddvm1),00h
(lcdhsp),284
(lcdvsp),324
(lcdprvsp),0
(lcdhsdly),11
(lcdlddly),096h
(lcdo0dly),16
(lcdhsw),7
(lcdldw),1
(lcdho0w),66
(lcdhwb8),0
(lsaml),400000h
0,(lcdctl0)
11LCP0
1
22LCP0
16LCP0
8LCP0
2
92CF26A-577
2LCP0
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
1
67LCP
VRAM:SDRAM, f
320com,240seg
PIP-OFF, Divide Frame ON: Line
LCP0 negedge, LHSYNC negedge, LVSYNC negedge, LLOAD
posedge
LGOE posedge
divide Line=1
LHSYNC cycle (LCP0*285)
LVSYNC cycle(LHSYNC*325)
Frame Rate=12.5ns*16*285*325 (54Hz)
LHSYNC delay=11*LCP0
LLOAD delay=22*LCP0, <PDT>=1
LHSYNC enable width=8*LCP0
LLOAD enable width=2*LCP0
main area start address set
LCDC start
Vertical front porch=0
LGOE0 delay=16*LCP0
LGOE enable width=67*LCP0
2
285LCP0
3
SYS
320
*16-clk, TFT256K color
SYS
=80MHz)
240
5LCP0
325
TMP92CF26A
2009-06-25
1