TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 581

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

TSICR0
(01F0H)
TSICR1
(01F1H)
3.20.2
bit Symbol
Read/Write
Reset State
Function
bit Symbol
Read/Write
Reset State
Function
PXD (internal pull-down resistor) ON/OFF setting
<TSI7>
Note1: Since the CPU clock is used for the debounce circuit, the debounce circuit does not operate and also no
Note2: To avoid a flow-through current to the normal C-MOS input gate when converting analog input data by using
Note3: For example:
<
PXEN
Touch Screen Interface (TSI) Control Register
0
1
interrupts that bypass the debounce circuit are generated during IDLE1and STOP mode, or the PCM state.
During IDLE1 or STOP mode, set this circuit to disable (Write “0” in TSICR1<DBC7>) before entering the
HALT stateIf debounce time is set to “0”, the signal is captured into the inside after a count of 6 system clocks
(f
the AD converter, TSICR0<INGE> can be controlled. If the intermediate voltage is input, cut the input signal to
the C-MOS logic (P96,P97) by setting this bit. TSICR0<PTST> is to confirm the initial pen-touch. Note that,
when the input to the C-MOS logic is blocked by TSICR0<INGE>, this bit is always “1”.
0: Disable
1: Enable
0: Disable
1: Enable
>
TSICR1=95H →N = 64 + 4 + 1 = 69, if set to (TSICR1) = 95 h
SYS
DBC7
TSI7
7
7
0
0
) from the point when this circuit is set to disable.
OFF
ON
0
R/W
Input gate
control of
Port 96,97
0: Enable
1: Disable
DB1024
INGE
1024
6
6
0
0
“N” is the number of bits between bit6 and bit0 which are set to “1”. Note3:
OFF
OFF
1
Detection
condition
0: no touch
1: touch
Debounce time setting register
DB256
PTST
Debounce time is set by the formula “(N*64-16) / f
256
R
5
0
5
0
TSI control register
92CF26A-579
INT4
interrupt
control
0: Disable
1: Enable
TWIEN
DB64
64
4
0
4
0
R/W
SPY
0 : OFF
1 : ON
PYEN
DB8
3
0
8
3
0
SPX
0 : OFF
1 : ON
PXEN
DB4
R/W
2
0
4
2
0
SMY
0 : OFF
1 : ON
SYS
MYEN
DB2
1
0
2
”.
1
0
SMX
0 : OFF
1 : ON
TMP92CF26A
DB1
MXEN
0
0
1
0
0
2009-06-25