TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 613

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

ADMOD2
(12BAH)
ADMOD3
(12BBH)
bit Symbol
Read/Write
Reset State
Function
bit Symbol
Read/Write
Reset State
Function
AD Mode Control Register 2 (Top-priority conversion control)
AD Mode Control Register 3 (Top-priority conversion control)
0: During
or before
1: Complete
Always
write “0”.
Top-priority
AD
conversion
sequence
FLAG
conversion
sequence
starting
conversion
sequence
HEOS
7
7
0
−
0
R
Figure 3.23.4 AD Conversion Registers
0:Stop
1:During
Top-priority analog input channel
select
Top-priority
AD
conversion
BUSY Flag
HADCH2
conversion
conversion
HBUSY
6
6
0
0
R/W
HADCH1
92CF26A-611
5
5
0
Analog input channel select
<HADCH2:0>
000
001
010
011
100
101
110
111
Note: When using PG3 pin as
HADCH0
4
4
0
0: Don’t Care
1: Start AD
Start
Top-priority
AD
conversion
Always read
as”0”.
conversion
HADS
3
0
3
Analog input
channel when
High-priority
conversion
AN0
AN1
AN2
AN3(note)
AN4
AN5
Reserved
Reserved
Top-priority
AD
conversion
at Hard
ware trigger
0: Disable
1: Enable
HHTRGE
ADTRG
2
2
0
R/W
, it cannot be set.
Select Hard ware trigger
00: INTTB10 interrupt
01: Reserved
10:
11: I
Output
HTSEL1
ADTRG
2
1
1
0
S Sampling Counter
TMP92CF26A
Always
write “0”.
2009-06-25
HTSEL0
R/W
0
0
0
−
0