TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 618

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

ADREGSPL
(12B0H)
ADREGSPH
(12B1H)
Channel X conversion
result
bit Symbol
Read/Write
Reset State
Function
bit Symbol
Read/Write
Reset State
Function
•
•
•
“1”. When Lower register (ADRECxL) is read, this bit is cleared to “0”.
ADREGxH/L before both the ADREGxH and ADREGxL are read. This bit is cleared to “0” by reading Flag.
Bits 5 ∼ 2 are always read as “0”.
Bit 0 is the AD conversion result store flag <ADRxRF>. When AD conversion result is stored, the flag is set to
Bit 1 is the Overrun flag <OVRx>. This bit is set to “1” if a next conversion result is written to the
Store Lower 2 bits of an
ADRSP1
ADRSP9
AD conversion result
7
7
0
Top-priority AD Conversion Result Register SP High
0
Top-priority AD Conversion Result Register SP Low
R
Figure 3.23.9 AD Conversion Registers
ADREGxH
ADRSP0
ADRSP8
9
6
6
7
0
0
8
6
7
ADRSP7
5
Store Upper 8 bits of an AD conversion result
92CF26A-616
5
5
0
4
6
3
5
ADRSP6
2
4
4
4
0
1
3
R
0
ADRSP5
2
3
3
0
1
7
0
6
ADRSP4
5
2
2
0
4
3
0:No
1: Generate
Overrun
flag
ADRSP3
generate
OVSRP
2
1
1
0
0
ADREGxL
1
TMP92CF26A
R
ADRSPRF
AD
conversion
result store
flag
1: Stored
ADRSP2
0
2009-06-25
0
0
0
0