TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 626

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

3.23.2.5 Top-Priority Conversion Mode
3.23.2.6 AD Monitor Function
3.23.2.7 AD Conversion Time
conversion start trigger
Conversion channel
Top-priority AD
Example: When AN5 top-priority AD conversion is started up with ADMOD3<HADCH2:0> = "101" during repeat
AD conversion sequence. A Top-priority AD conversion can be started at software by
setting the ADMOD2<HADS> to “1”. It is also triggered by a hardware trigger if so
enabled using ADMOD2<HTSEL1:0>. If a Top-priority AD conversion is triggered
during a normal AD conversion, the ADC aborts any ongoing conversion immediately,
and then begins a single Top-priority AD conversion for the channel specified with the
ADMOD3<HADC2:0>. Upon the completion of the Top-priority AD conversion, the
ADC stores the results of the conversion in the ADREGSPH/L, generates the
Top-priority AD conversion interrupt (INTADHP), and then resumes the suspended
normal conversion with that channel. While a Top-priority conversion is being
performed, a trigger for another Top-priority conversion is ignored.
the value of AD conversion result register (H/L), ADMOD4<CMP1C:0C> can select
greater or smaller of comparison format. As register ADMOD4<IRQEN1:0> is Enable,
corresponding conversion result storage register. When conditions are met, the
interrupt is generated. Be careful that the storage registers assigned for the AD
monitoring function are usually not ready by software, which means that the overrun
flag <OVRx> is always set and the conversion result storage flag <ADRxRF> is also
set.
smaller is possible in the two analog channels. In addition, if assigned to the same
channels, the monitoring with the voltage range set is possible.
clock is selected from 1/1 to 1/7 f
accuracy, the AD conversion clock needs to be set to 12 MHz or less; or equivalently 10
μs or more of AD conversion time.
scan conversion at channels AN0 to AN3 with ADMOD1<REPEAT, SCAN> = "11" and
ADMOD1<ADCH2:0> = "011"
Setting ADMOD4<CMEN1:0> to 1 enables the AD monitoring function.
The value of Result storage register that is appointed by ADMOD5 is compared with
This comparison operation is performed each time when a result is stored in the
If each of them is assigned to separate channels, the monitoring of greater or
One AD conversion takes 120 clocks including sampling clocks. The AD conversion
The ADC can perform a Top-priority AD conversion while it is performing a normal
AN0
AN1
92CF26A-624
AN2 conversion
canceled
IO
AN2
by ADCLK <ADCLK2:0>. To meet the guaranteed
AN5 conversion started
AN5
AN2 re-conversion
started
AN2
AN3
TMP92CF26A
2009-06-25
AN0