TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 629

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

3.24 Watchdog Timer (Runaway detection timer)
3.24.1
the CPU has started to malfunction (runaway) due to causes such as noise. When the watchdog
timer detects a malfunction, it generates a non-maskable interrupt INTWD to notify the CPU of
the malfunction.
The TMP92CF26A contains a watchdog timer of runaway detecting.
The watchdog timer (WDT) is used to return the CPU to the normal state when it detects that
Connecting the watchdog timer output to the reset pin internally forces a reset.
(The level of external
Internal reset
Note: Care must be exercised in the overall design of the apparatus since the watchdog timer may fail to function
Configuration
Figure 3.24.1 is a block diagram of the watchdog timer (WDT).
correctly due to external noise, etc.
f
IO
<WDTP1:0>
WDMOD
Figure 3.24.1 Block Diagram of Watchdog Timer
RESET
Binary counter
(22 stages)
2
15
WDT control register WDCR
pin is not changed.)
Selector
2
Write
4EH
Reset
17
92CF26A-627
2
Internal data bus
19
2
21
Write
B1H
WDMOD<RESCR>
R
Reset control
Q
WDMOD
<WDTE>
S
INTWD interrupt
Internal reset
TMP92CF26A
RESET
2009-06-25
pin