TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 634

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

PMCCTL
(02F0H)
3.25.1
Bit Symbol
Read/Write
System
Reset State
Hot Reset
State
Function
External interrupt input
Operation after reset
Operation after hot reset
Warm-up counter
Note1: About 77 μs after a wake-up interrupt has been requested, the external PWE terminal changes from low to
Note 2: This register should usually be set in the initial status (all bits are “0”). Writing should be made immediately
Special Function Register (SFR)
The operations depending on the setting of the PCM_ON bit are shown below.
high. At this point, the warm-up counter starts counting up the time period specified by the WUTM1 and
WUTM0 bits. Then, about 92 μs later, the internal reset signal is negated. The time required for the power
supply voltage to stabilize varies depending on the power supply response and the board conditions. This
characteristic should be considered in specifying the warm-up time.
before the power-cut mode is assumed. Reset the values of all registers to the initial status (all bits are “0”)
immediately after the power-cut mode. For details, refer to the flow of transition to the power cut status
described later.
Power Cut
Mode
1: Enable
0: Disable
PCM_ON
retained
Data
R/W
7
0
No interrupt
HOT_RESET signal asserted
Startup from the boot-ROM
regardless of the settings of the
AM1 and AM0 pins and a program
flow jumps to the specified
address in the on-chip RAM area.
A change in the PWE pin level is
used as a trigger to start counting
the low-frequency clock. Then
HOT_RESET signal negated.
6
PCM_ON = 1
92CF26A-632
5
−
4
Interrupt
Startup depending on the settings
of the AM1 and AM0 pins
3
PCM_ON = 0
Must be
written as
0
Always
read as 0
W
2
−
0
−
−
−
Warm-up Time
00: 2
01: 2
10: 2
11: 2
WUTM1
retained
Data
1
0
9
10
11
12
(15.625 ms)
(125 ms)
(31.25 ms)
(62.5 ms)
R/W
TMP92CF26A
WUTM0
retained
Data
2009-06-25
0
0