TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 636

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

1. Configurations Required for Entering the Power Cut Mode
2. Mode Transition Sequence
(1) Writing the boot program that is executed after the warm-up time has elapsed
(2) Controlling the low-frequency clock (XT)
(1) Program execution jumps to the on-chip RAM area.
(2) Configure the required port settings (through the Pn, PnCR, PnFC and PnDR
(3) Disable interrupts (DI)
(4) Stop the PLL operation
(5) Setup the warm-up time: PMCCTL<WUTM1:0>
boot-ROM program. All codes required for initializing registers including WDT
must be written in the fixed RAM area (46000Hto 49FFFH).
clock. Thus, the low-frequency clock (XT) must always be enabled.
transition must be disabled.
configured as rising-edge triggered.
disabled.
terminal changes from low to high. At this point, the warm-up counter starts
counting up the time period specified by the WUTM1 and WUTM0 bits. Then,
about 92 μs later, the internal reset signal is negated. The time required for the
power supply voltage to stabilize varies depending on the power supply response
and the board conditions. This characteristic should be considered in specifying the
warm-up time.
(46000Hto 49FFFH)
registers)
Program the high-frequency clock frequency f
operation.
a. Disable the Watch Dog Timer
b. Disable the A/D converter
c.
Only bit 7 of the PMCCTL register is checked whether it is 1 or 0 in the
Entering or exiting the Power Cut mode is performed using the low-frequency
Before entering the Power Cut mode, all the sources that might disturb the mode
All the external interrupt inputs usable for wake-up signaling must be
When the INT4 pin is used as the TSI input, the debounce circuit should be
About 77 μs after a wake-up interrupt has been requested, the external PWE
(Warm-up time can be selected from 15.625 ms, 31.25 ms, 62.5 ms and 125 ms.)
• Disable the LCDC
• Disable the auto-refresh function of SDRAM (switching to the self refresh
mode)
• Disable the HDMA function
Disable all the DMA functions of the system
92CF26A-634
SYS
to be f
OSCH
and stop the PLL
TMP92CF26A
2009-06-25