TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 639

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

CPU state transition
XT2
PMCCTL<PCM_ON>
PWE pin
INTRTC
INT0-7, INTKEY
Internal HOT_RESET
1. A maximum of 3 clock cycles (92
Port state
3.25.3
μs) are needed for entering PCM.
1.
2.
3.
4.
5.
Detailed Descriptions and Timing Considerations
Internal HOT_RESET assert to dead circuit only. (DVCC1A &DVCC1C circuit)
When PMCCTL<PCM_ON> = 1, mode transition from normal mode to the Power Cut
mode takes a maximum of three low-frequency clock cycles (about 92 μs). During this
period, the external wake-up requests are ignored.
A maximum of 2.5low-frequency clock cycles (about 77 μs) is required for the PWE pin to
change from 0 to 1 after the wake-up interrupt is received.
After exiting the Power Cut mode, the PMCCTL<PCM_ON> bit is cleared to 0 by soft
ware to return to normal mode. To enter the Power Cut mode again, the
PMCCTL<PCM_ON> bit should be once cleared to 0 and set to 1 again. In this case, the
PMCCTL<PCM _ON> bit should be fixed at 0 for a minimum of one low-frequency clock
cycle (about 31 μs). Otherwise, the PCM may not be entered by changing its state from 1
to 0 and to 1 again.
The wake-up triggers asserted during the wake-up operation from the PCM are ignored.
When a maximum of one low-frequency clock cycle (about 31 μs) has elapsed after the
warm-up counter is expired, the DRV setting of every port is switched to the normal
setting. Then, two low-frequency clock cycles (about 62 μs) later, the internal reset signal
(Hot_Reset) is negated.
Normal
1. This interrupt is ignored.
2. A maximum of 2.5 clock cycles (77 μs)
are needed after an interrupt is requested.
Interrupt enabled period
92CF26A-637
Drive register active period
Power Cut Mode (PCM)
4. These interrupts are
ignored.
3. A minimum of 1 clock cycle (31 μs)
is needed for entering PCM again.
Warm-up
3CLK
5. The drive register setting is
released a maximum of 1
clocks (31 μs) after the end of
warm-up.
TMP92CF26A
Normal
2009-06-25