TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 644

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

MACCR
(1BFCH)
A read-
modify-
write
operation
cannot be
performed
3.26 Multiply and Accumulate Calculation Unit (MAC)
3.26.1
3.26.1.1 Control Register
64-bit arithmetic operations at high speed. The MAC has the following features:
The TMP92CF26A includes a multiply-accumulate unit (MAC) capable of 32-bit × 32-bit +
bit Symbol
Read/Write
Reset State
Function
Note 1: <MOPST> is write-only and it is read as “0”.
Note 2: Writing “1xx” to <MSTTG2:0> and writing “1” to <MOPST> can be executed in the same write cycle.
Note 3: <MOVF> is fixed two system clocks (f
registers are connected to the CPU via a 32-bit bus and can be accessed in one system clock
(f
Registers
SYS
・ One-cycle execution for all MAC operations (excluding register access time)
・ Three operation modes :
・ Support for signed/unsigned operations
・ Support for integer operations only
The MAC in the TMP92CF26A has one control register and three data registers. These
).
The control register is used to control the operation of the MAC.
Overflow
flag
0: No
1: Overflow
overflow
occurred
MOVF
R/W
0
7
Calculation
soft start
0:Don’t care
1:Start
calculation
MOPST
W
0
6
MAC Control Register
Calculation start trigger
000: Write to MACMA<7:0>
001: Write to MACMB<7:0>
010: Write to MACMOR<7:0>
011: Write to MACMOR<39:32>
1xx: Write of “1” to <MOPST>
MSTTG2
92CF26A-640
2) 64-bit − 32-bit × 32-bit
3) 32-bit × 32-bit − 64-bit
5
0
1) 64-bit + 32-bit × 32-bit
SYS
) after calculation is started.
MSTTG1
4
0
MSTTG0
3
0
R/W
Sign mode
0: Unsigned
1: Signed
MSGMD
2
0
Calculation mode
00: 64 + 32×32
01: 64 − 32×32
10: 32×32 − 64
11: Reserved
MOPMD1
0
1
TMP92CF26A
MOPMD0
2009-06-25
0
0