TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 652

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

PUDR
(009CH)
PUFC
(00A7H)
PUCR
(00A6H)
PU
(00A4H)
Bit Symbol
Read/Write
Reset State
Bit Symbol
Read/Write
Reset State
Function
Bit Symbol
Read/Write
Reset State
Function
Bit Symbol
Read/Write
Reset State
Function
Note: Although it is possible to write to shaded bits, writing to these bits has no effect (the DSU communication
function is given a higher priority).
PU7C
PU7F
PU7D
PU7
7
7
7
7
0
0
1
PU6C
PU6D
PU6F
PU6
6
6
6
6
0
0
1
Port U Function Register
External pin data (Output latch is reset to “0”.)
Port U Control Register
PU5C
PU5D
PU5F
Note: When LD23 to LD16 are used, set <PUnC> to “1”.
Port U Drive Register
PU5
5
5
5
5
0
0
1
Input/output buffer drive register for standby mode
92CF26A-650
Port U Register
0: Port 1: Data bus for LCDC (LD23 to LD16)
PU4D
PU4C
PU4F
0: Input 1: Output
PU4
4
4
4
4
0
0
1
R/W
PU3C
PU3D
PU3F
PU3
R/W
W
W
3
3
3
0
3
0
1
PU2C
PU2D
PU2F
PU2
2
2
2
0
2
0
1
PU1C
PU1F
PU1D
PU1
1
1
1
0
0
1
1
TMP92CF26A
PU0D
PU0C
PU0F
PU0
0
0
0
1
0
0
0
2009-06-25