TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 664

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

Note1: The phase relation between X1 input signal and the other signals is undefined.
Note2: The above timing chart show an example of basic bus timing. The
D0~D15
A0~A23
SDCLK
SRWR
SRxxB
WRxx
WAIT
R/
CSn
RD
pins timing can be adjusted by memory controller timing adjust function.
X1
(2) Write cycle (0 waits)
W
t
t
t
SAS
AW
CL
t
RDO
t
OSC
t
CYC
92CF26A-662
t
WK
t
CH
t
t
t
SDS
t
SBW
SWP
TK
t
KT
Data output
t
t
WW
DW
CSn
, R/ W ,
t
t
t
SWR
t
WA
SDH
WD
RD
,
WRxx
,
TMP92CF26A
SRxxB
2009-06-25
,
SRWR