TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 666

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

AC measuring condition
No.
4.3.2
1 System clock period ( = T)
2 A0, A1
3 A2 ~ A23
4
5 A0 ~ A23 Invalid → D0 ~ D15 hold
6
D0~D15
A0~A23
SDCLK
RD
RD
CS
RD
Note: The (a), (b) and (c) of “Symbol” in above table depend on the falling timing of RD pin. The falling timing of RD
falling
rising
2
Page ROM Read Cycle
(1) 3-2-2-2 mode
pin is set by MEMCR0<RDTMG1:0> in memory controller. If MEMCR0<RDTMG1:0> is set to “00”, it correspond
with (a) in above table, and “01” is (b), “10” is (c).
Parameter
Page Mode Access Timing (when using a 8-byte page size example)
t
CYC
→ D0 ~ D15 input
→ D0 ~ D15 input
→ D0 ~ D15 input
→ D0 ~ D15 hold
t
AD3
t
RD3
+ 0
Data
input
Symbol
t
t
t
t
t
CYC
AD2
AD3
RD3
t
HR
HA
92CF26A-664
t
t
HA
AD2
+ 2
Min
12.5
0
0
Data
input
Variable
2.0T − 18
3.0T − 18
2.5T − 18
t
Max
t
2666
HA
AD2
+ 4
Data
input
80 MHz 60 MHz
12.5
19.5
13
7
0
0
t
t
HA
AD2
+ 6
16.6
15.2
31.8
24
0
0
Data
input
TMP92CF26A
Unit
t
t
ns
HA
HR
2009-06-25