TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 677

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

LCP0 clock period
LCP0 high width
(Include phase inversion)
LCP0 low width
(Include phase inversion)
Data valid → LCP0 falling
(Include phase inversion)
LCP0 falling  → Data hold
(Include phase inversion)
Signal delay from LCP0 basic
changing point
(Include phase inversion)
4.3.9
AC measuring condition
• C
Parameter
Note: The “n” in “Variable” show value that is set to LCDMODE0<SCPW1:0>.
L
LCD Controller
= 50 pF (LCP0 only C
Example: If LCDMODE0<SCPW1:0> = “01”, n = 1, t
LD0~LD23
LHSYNC
LVSYNC
LGOE0
LGOE1
LGOE2
LLOAD
LDINV
LCP0
FR
Symbol
t
t
t
t
t
t
CWH
CWL
DSU
DHD
GDL
CW
L
= 30 pF)
t
t
CWH
DSU
LD0~LD23 out
t
GDL
T(n + 1) − 7.5
T(n + 1) − 7.5
92CF26A-675
T(n + 1) − 5
T(n + 1) − 5
2T(n + 1)
LDINV
Min
-15
t
CW
t
t
CWL
DHD
Variable
RWP
= 2T(n + 1) = 2T
Max
15
80 MHz
(n=0)
± 15
7.5
7.5
25
5
5
60 MHz
(n=0)
± 15
33.3
11.6
11.6
9.1
9.1
TMP92CF26A
2009-06-25
Unit
ns