TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 695

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

Symbol
PA
PC
PG
P1
P4
P5
P6
P7
P8
P9
PF
PJ
(1) I/O ports (1/11)
PORT1
PORT4
PORT5
PORT6
PORT7
PORT8
PORT9
PORTA
PORTC
PORTF
PORTG
PORTJ
Note: If it is started at boot mode (AM [1:0] = “11”), output latch of P82 is set to “1”.
Name
Address
001CH
003CH
004CH
0004H
0010H
0014H
0018H
0020H
0024H
0028H
0030H
0040H
Data from external port
PC7
R/W
PA7
PF7
P17
P47
P57
P67
P87
P97
PJ7
7
0
−
0
−
1
−
1
−
1
−
R
−
(Output latch register is
(Output latch register is
Data from external port
Data from external port
PC6
P16
P46
P56
P66
P76
P86
P96
PA6
PJ6
6
−
−
−
Data from external port (Output latch register is cleared to “0”)
0
0
Data from external port (Output latch register is cleared to “0”)
1
set to “1”)
set to “1”)
Data from external port (Output latch register is set to “1”)
92CF26A-693
−
−
PC5
PG5
PA5
PF5
P15
P45
P55
P65
P75
P85
PJ5
5
0
−
0
−
1
−
Data from external port (Output latch register is set to “1”)
(Output latch register is
Data from external port
Data from external port
PG4
PA4
PC4
P14
P44
P54
P64
P74
P84
PF4
PJ4
cleared to “0”)
4
0
−
0
−
1
−
1
−
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
−
−
−
−
−
Data from external port
R/W
PA3
PC3
PG3
P13
P43
P53
P63
P73
P83
PF3
PJ3
3
−
−
−
−
0
0
1
1
R/W
R
−
−
(Output latch register is
Data from external port
(Output latch register is set to “1”)
0 (Note)
PA2
PC2
PG2
P12
P42
P52
P62
P72
P82
P92
PF2
PJ2
2
−
−
−
−
0
0
1
Data from external port
set to “1”)
−
R/W
PA1
PC1
PG1
P11
P41
P51
P61
P71
P81
P91
PF1
PJ1
1
−
−
−
−
−
0
0
1
1
TMP92CF26A
2009-06-25
PC0
PG0
P10
P40
P50
P60
P70
P80
P90
PA0
PF0
PJ0
0
−
−
−
−
−
0
0
1
1
1