TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 70

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

3.5.1
operations. However, in the case of software interrupts and illegal instruction interrupts
generated by the CPU, the CPU skips steps (1) and (3), and executes only steps (2), (4), and
(5).
the main routine. RETI restores the contents of the program counter and the status
register from the stack and decrements the interrupt nesting counter INTNEST by 1.
however, can be enabled or disabled by a user program. A program can set the priority level
for each interrupt source. (A priority level setting of 0 or 7 will disable an interrupt
request.) If an interrupt request is received for an interrupt with a priority level equal to or
greater than the value set in the CPU interrupt mask register <IFF2:0>, the CPU will
accept the interrupt. The CPU interrupt mask register <IFF2:0> is then set to the value of
the priority level for the accepted interrupt plus 1.
interrupt currently being processed, or if, during the processing of a non-maskable
interrupt processing, a non-maskable interrupt request is generated from another source,
the CPU will suspend the routine which it is currently executing and accept the new
interrupt. When processing of the new interrupt has been completed, the CPU will resume
processing of the suspended interrupt.
the new interrupt will be sampled immediately after execution of the first instruction of its
interrupt processing routine. Specifying DI as the start instruction disables nesting of
maskable interrupts.
interrupts.
FFFF00H to FFFFFFH (256 bytes) is designated as the interrupt vector area.
(1) The CPU reads the interrupt vector from the interrupt controller. When more than one
(2) The CPU pushes the program counter (PC) and status register (SR) onto the top of the
(3) The CPU sets the value of the CPU’s interrupt mask register <IFF2:0> to the priority
(4) The CPU increments the interrupt nesting counter INTNEST by 1.
(5) The CPU jumps to the address given by adding the contents of address FFFF00H + the
When the CPU accepts an interrupt, it usually performs the following sequence of
On completion of interrupt processing, the RETI instruction is used to return control to
Non-maskable interrupts cannot be disabled by a user program. Maskable interrupts,
If during interrupt processing, an interrupt is generated with a higher priority than the
If the CPU receives another interrupt request while performing processing steps (1) to (5),
A reset initializes the interrupt mask register <IFF2:0> to 111, disabling all maskable
Table 3.5.1 shows the TMP92CF26A interrupt vectors and micro DMA start vectors.
General-purpose Interrupt Processing
interrupt with the same priority level has been generated simultaneously, the interrupt
controller generates an interrupt vector in accordance with the default priority and
clears the interrupt requests. (The default priority is determined as follows: The
smaller the vector value, the higher the priority.)
stack (Pointed to by XSP).
level for the accepted interrupt plus 1. However, if the priority level for the accepted
interrupt is 7, the register’s value is set to 7.
interrupt vector, then starts the interrupt processing routine.
92CF26A-68
TMP92CF26A
2009-06-25