TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 717

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

LCDPRVSP
LCDHSDLY
LCDLDDLY
LCDCTL2
Symbol
LCDCTL1
LCDHSP
LCDHSP
LCDVSP
LCDVSP
(6) LCD controller (2/4)
LCD
control1
register
LCD
control2
register
LHSYNC
Pulse
register
LHSYNC
Pulse
register
LVSYNC
Pulse
register
LVSYNC
Pulse
register
LVSYNC
Pre Pulse
register
LHSYNC
Delay
register
LLOAD
Delay
register
Name
Address
028CH
028DH
028AH
028BH
028EH
028FH
0286H
0287H
0290H
Data output
timing
0: Sync with
1: 1 clock
LCP0
phase
0:Rising
1:Falling
LGOE2
phase
0: Rising
1: Falling
LGOE2P
LLOAD
later than
LLOAD
LCP0P
PDT
R/W
LH15
LVP7
R/W
LH7
7
1
0
0
0
0
0
LGOE1
phase
0: Rising
1: Falling
LHSYNC
phase
0:Rising
1: Falling
LGOE1P
HSD6
LHSP
PLV6
LDD6
R/W
R/W
LH14
LVP6
LH6
6
0
0
0
0
0
0
0
0
92CF26A-715
LVSYNC
phase
0:Rising
1: Falling
LGOE0
phase
0: Rising
1: Falling
LGOE0P
LVSP
HSD5
LDD5
PLV5
R/W
LH13
LVP5
LH5
5
1
0
0
0
0
0
0
0
LHSYNC period (bits 15-8)
LHSYNC period (bits 7-0)
LVSYNC period (bits 7-0)
LLOAD
phase
0:Rising
1: Falling
Front dummy LVSYNC (bits 6-0)
HSD4
LLDP
LDD4
PLV4
R/W
LVP4
LH12
LH4
4
0
0
0
0
LHSYNC delay (bits 6-0)
0
0
0
LLOAD delay (bits 6-0)
W
W
W
HSD3
PLV3
LDD3
LH11
LVP3
LH3
W
W
W
3
0
0
0
0
0
0
HSD2
LDD2
PLV2
LVP2
LH10
LH2
2
0
0
0
0
0
0
LVSYNC
enable time control
00: 1 clock of LHSYNC
01: 2 clocks of LHSYNC
10: 3 clocks of LHSYNC
11: Reserved
LVSW1
HSD1
LDD1
LVP9
PLV1
R/W
LVP1
LVSYNC period
TMP92CF26A
LH1
LH9
1
0
0
0
0
0
0
0
0
(bits 9-8)
2009-06-25
W
LVSW0
HSD0
LDD0
LVP8
PLV0
R/W
LVP0
LH0
LH8
0
0
0
0
0
0
0
0
0