TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 718

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

LCDO0DLY
LCDO1DLY
LCDO2DLY
Symbol
LCDHSW
LCDHO0W
LCDHO1W
LCDHO2W
LCDLDW
LCDHWB8
(6) LCD controller (3/4)
LGOE0
Delay
register
LGOE1
Delay
register
LGOE2
Delay
register
LHSYNC
Width
register
LLOAD
width
register
LGOE0
width
register
LGOE1
width
register
LGOE2
width
register
Bit8,9
for signal
width
register
Name
Address
0291H
0292H
0293H
0294H
0295H
0296H
0297H
0298H
0299H
HSW7
O0W7
O1W7
O2W7
O2W9
LDW7
7
0
0
0
0
0
0
LGOE2 width
(bits 9-8)
OE0D6
OE1D6
OE2D6
HSW6
LDW6
O0W6
O1W6
O2W6
O2W8
6
0
0
0
0
0
0
0
0
0
92CF26A-716
OE0D5
OE1D5
OE2D5
HSW5
LDW5
O0W5
O1W5
O2W5
O1W9
5
0
0
0
0
0
0
0
0
0
LGOE1 width
(bits 9-8)
Setting bit7-0 for LHSYNC Width
LHSYNC width (bits 7-0)
LLOAD width (bits 7-0)
LGOE1 width (bits 7-0)
LGOE2 width (bits 7-0)
OE0D4
OE1D4
OE2D4
HSW4
O0W4
O1W4
O2W4
O1W8
LDW4
4
0
0
0
0
0
0
0
0
0
OE0 delay (bits 6-0)
OE1 delay (bits 6-0)
OE2 delay (bits 6-0)
W
W
W
W
W
W
OE0D3
OE1D3
OE2D3
LGOE0
HSW3
LDW3
O0W3
O1W3
O2W3
O0W8
(bit 8)
width
W
W
W
3
0
0
0
0
0
0
0
0
0
LLOAD width (bits 9-8)
OE0D2
OE1D2
OE2D2
HSW2
O0W2
O1W2
O2W2
LDW2
LDW9
2
0
0
0
0
0
0
0
0
0
OE0D1
OE1D1
OE2D1
HSW1
O0W1
O1W1
O2W1
LDW1
LDW8
TMP92CF26A
1
0
0
0
0
0
0
0
0
0
2009-06-25
LHSYNC
OE0D0
OE1D0
OE2D0
HSW0
O0W0
O1W0
O2W0
HSW8
LDW0
(bit 8)
width
0
0
0
0
0
0
0
0
0
0