TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 75

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

Symbol
DMAR
DMA
Request
Name
(2) Soft start function
(3) Transfer control registers
Note1: If it is started by software, don’t set any channels to start in same time.
Note2: If be started sequentially, restart it after confirming micro DMA of all channels is completed (all micro DMA are
using the micro DMA /HDMA soft start function, in which micro DMA or HDMA is
initiated by a Write cycle which writes to the register DMAR.
performed once (If write “0” to each bit, micro DMA doesn’t operate). On completion of
the transfer, the bits of DMAR for the completed channel are automatically cleared to
“0”.
transfer counter (DMACn) or HDMA transfer counter B (HDMACBn) become “0”.
from the initiation of micro DMA until the value in the micro DMA transfer counter is
“0”. If execatee soft start during micro DMA transfer by interrupt source, micro DMA
transfer counter doesn’t change. Don’t use Read-modify-write instruction to avoid
writign to other bits by mistake.
following registers. An instruction of the form LDC cr,r can be used to set these
registers.
set to “0”).
Address
The TMP92CF26A can initiate micro DMA/HDMA either with an interrupt or by
Writing “1” to each bit of DMAR register causes micro DMA or HDMA to be
When writing again “1” to it, soft start can execute continuously until the DMA
When a burst is specified by the register DMAB, data is transferred continuously
The transfer source address and the transfer destination address are set in the
(Prohibit
RMW)
109H
Channel 0
Channel 7
DMAS0
DMAD0
DMAS7
DMAD7
32 bits
DREQ7
DMAC0
DMAC7
7
0
16 bits
DMAM0
DMAM7
8 bits
DREQ6
6
0
92CF26A-73
Micro DMA source address register 0
Micro DMA destination address register 0
Micro DMA counter register 0
Micro DMA mode register 0
Micro DMA source address register 7
Micro DMA destination address register 7
Micro DMA counter register 7
Micro DMA mode register 7
DREQ5
5
0
DREQ4
4
0
1: Start DMA
R/W
DREQ3
3
0
DREQ2
2
0
DREQ1
TMP92CF26A
1
0
2009-06-25
DREQ0
0
0