TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 751

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

TB0RG0H
TB0RG1H
TB0FFCR
TB0CP0H
TB0CP1H
TB0RG0L
TB0RG1L
TB0CP0L
TB0CP1L
Symbol
TB0MOD
TB0RUN
(15) 16-bit timer (1/2)
TMRB0
RUN
register
TMRB0
MODE
register
TMRB0
Flip-Flop
control
register
16 bit timer
register 0
low
16 bit timer
register 0
high
16 bit timer
register low
16 bit timer
register 1
high
Capture
register 0
low
Capture
register 0
high
Capture
register 1
low
Capture
register 1
high
Name
Address
(Prohibit
(Prohibit
(Prohibit
(Prohibit
(Prohibit
(Prohibit
118AH
118BH
118CH
118DH
118EH
1180H
1182H
1183H
1188H
1189H
118FH
RMW)
RMW)
RMW)
RMW)
RMW)
RMW)
Double
buffer
0: disable
1: enable
Always write “00”.
Always write “11”.
* Always read as “11”.
TB0RDE
R/W
7
0
−
0
−
1
R/W
W*
Always
write “0”.
R/W
6
−
0
−
0
−
1
92CF26A-749
Software
capture
control
0: Execute
1:Undefined
TB1FF0 inversion trigger
0: Disable trigger
1: Enable trigger
When
capture
UC10 to
TB0CP1H/L
TB0CP0I
TB0CT1
W*
5
1
0
Capture timing
00: Disable
01: TB0IN0 ↑
10: TB0IN0 ↑ TB0IN0 ↓
When
capture
UC10 to
TB0CP0H/L
TB0CPM1 TB0CPM0
11: TA1OUT ↑
TB0C0T1
TA1OUT ↓
INT6 occurs at rising
edge
INT6 occurs at rising
edge
INT6 occurs at rising
edge
INT6 occurs at falling
edge
4
0
0
Undefined
Undefined
Undefined
Undefined
R/W
W
W
W
W
R
R
R
R
−
0
−
0
−
0
−
0
−
−
−
−
When UC10
matches with
TB0RG1H/L
IDLE2
0: Stop
1: Operate
TB0E1T1
I2TB0
R/W
3
0
0
0
TMRB0
prescaler
0: Stop and clear
1: Run (Count up)
Control Up
counter
0:Clear
1:Clear
When UC10
matches with
TB0RG0H/L
TB0PRUN
TB0E0T1 TB0FF0C1 TB0FF0C0
TB0CLE
Disable
Enable
R/W
R/W
2
0
0
0
TMRB1 source clock
00: TB0IN0 input
01: φ T1
10: φ T4
11: φ T16
Control TB1FF0
00: Invert
01: Set
10: Clear
11: Don’t care
* Always read as “11”.
TB0CLK1 TB0CLK0
TMP92CF26A
1
0
1
2009-06-25
W*
Up counter
(UC10)
TB0RUN
R/W
0
0
0
1