TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 757

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

ADMOD1
ADMOD2
ADMOD3
ADMOD4
ADMOD5
Symbol
ADCCLK
(18) AD converter (3/3)
AD
Conversion
Clock
Setting
Register
AD mode
control
register 1
AD mode
control
register 2
AD mode
control
register 3
AD mode
control
register 4
AD mode
control
register 5
Name
Address
12BFH
12BCH
12BDH
12B9H
12BAH
12BBH
DAC and
VREF
application
control
High-priority
AD
conversion
sequence
FLAG
0: During
1: Complete
Always write
“0”.
AD Monitor
function1
0: Disable
1: Enable
conversion
sequence
or before
starting
conversion
sequence
DACON
CMEN1
HEOS
7
0
0
−
0
0
R
High-priority
AD
conversion
BUSY Flag
0:Stop
1:During
High-priority analog input channel select
AD Monitor
function0
0: Disable
1: Enable
Select analog channel for AD monitor
function 1
000: AN0
001: AN1
010: AN2
011: AN3
HADCH2
CM1CH2
conversion
conversion
CMEN0
ADCH2
HBUSY
6
0
0
0
0
0
Analog input channel select
92CF26A-755
R/W
Generation
condition of
AD monitor
function
interrupt 1
0: less than
1: Greater
HADCH1
CM1CH1
than or
Equal
100: AN4
101: AN5
110: Reserved
ADCH1
CMP1C
111: Reserved
R/W
5
0
0
0
0
R/W
Generation
condition of
AD monitor
function
interrupt 0
0: less than
1: Greater
HADCH0
CM1CH0
than or
Equal
CMP0C
ADCH0
4
0
0
0
0
R/W
Latency
0: No Wait
1:Start after
Start
High-priority
AD
conversion
0: Don’t Care
1: Start AD
Always read
AD monitor
function
interrupt 1
0: Disable
1: Enable
Always
write “0”
reading
conversion
result store
Register of
last
channel
conversion
as”0”.
IRQEN1
HADS
R/W
LAT
3
0
0
0
−
0
Interrupt
specification
when
conversion
channel fixed
repeat mode
High-priority
AD
conversion at
Hard ware
trigger
0: Disable
1: Enable
AD monitor
function
interrupt 0
0: Disable
1: Enable
Select analog channel for AD monitor
function 0
000: AN0
001: AN1
010: AN2
011: AN3
Select clock for AD conversion
000 : Reserved
001 : f
010 : f
011 : f
HHTRGE
CM0CH2
ADCLK2
IRQEN0
R/W
ITM
2
0
0
0
0
0
IO
IO
IO
/1
/2
/3
R/W
Repeat
mode
specification
0:Single
1:Repeat
Select Hard ware trigger
00: INTTB10 interrupt
01: Reserved
10:
11: I
Status of
AD monitor
function
interrupt 1
0: No
1:
CMPINT1
CM0CH1
REPEAT
HTSEL1
ADCLK1
conversion
conversion
Output
generation
Generation
100: AN4
101: AN5
110: Reserved
111: Reserved
R/W
ADTRG
2
R/W
S Sampling Counter
1
0
0
0
0
0
100 : f
TMP92CF26A
101 : f
110 : f
111 : f
2009-06-25
Scan mode
specification
0: Channel
1: Channel
Always write
“0”.
Status of
monitor
function
interrupt 0
0: No
1: Generation
IO
IO
IO
IO
CMPINT0
fixed mode
scan mode
generation
CM0CH0
HTSEL0
ADCLK0
/4
/5
/6
/7
SCAN
R/W
R/W
0
0
0
−
0
0
0
0
AD